Location: Bangalore, India
Company: [Your Company Name or Broadcom, if applicable]
Job Type: Full-time | Senior Level | VLSI/Physical Design | Semiconductor
Job Overview:
We are seeking a Senior Memory Layout Design Engineer with deep expertise in CMOS memory layout design, physical verification, and advanced process nodes (16nm, 7nm, 5nm, 3nm). This is a key role within our semiconductor design team, responsible for developing high-quality, optimized memory layouts and guiding the team through evolving design methodologies and technology nodes. If you are passionate about physical design, thrive in a fast-paced environment, and are ready to take technical ownership, we’d love to hear from you.
Key Responsibilities:
- Design high-quality layouts for standard cells, I/Os, memories, and related digital blocks in advanced nodes.
- Execute and manage floorplanning, layout hierarchy planning, and integration of complex memory blocks.
- Ensure clean LVS, DRC, ERC, Antenna, and ElectroMigration (EM) compliance using industry tools (e.g., Calibre, Hercules).
- Apply and adapt to new layout methodologies and technology rules across leading-edge process technologies (down to 3nm).
- Contribute to or lead memory compiler layout implementation and design flow development.
- Collaborate closely with design, verification, and integration teams to ensure quality and timely project delivery.
- Lead layout reviews, documentation, and best practices definition for layout guidelines and flows.
- Mentor and support junior layout engineers to ensure high productivity and skills development.
Required Qualifications:
- 6 to 10 years of hands-on experience in memory and digital layout design.
- Bachelor’s degree in Electronics, Electrical Engineering, or related field.
- Expertise in Cadence Virtuoso (XL, VXL, or EXL) layout tools and CALIBRE verification tools.
- In-depth understanding of CMOS process rules and layout best practices for deep submicron nodes (16nm and below).
- Proficient in physical verification (LVS, DRC, ERC, Antenna, EM).
- Strong experience in hierarchical layout, chip integration, and floorplanning.
- Familiarity with layout for memory topologies and standard cell designs.
- Solid communication and documentation skills with the ability to work independently or in a team.
Preferred Skills:
- Experience in analog layout is a plus.
- Prior involvement in memory compiler development is highly desirable.
- Familiarity with SKILL or script programming for layout automation.
- Demonstrated leadership in project management or team mentorship.
What We Offer:
- Opportunity to work on next-gen semiconductor technologies.
- A collaborative environment that values innovation, precision, and continuous learning.
- Competitive compensation and benefits.
- A strong platform for career advancement and technical leadership.