Location: Bengaluru
Department: Physical Layer Products Group – High-Speed SerDes Team
Job Type: Full-time
About the Role:
We are seeking a highly skilled and efficient Senior Design Verification Engineer to join our High-Speed SerDes Team within the Physical Layer Products Group at Broadcom. This is an excellent opportunity for experienced verification professionals to work on cutting-edge Ethernet and SerDes technologies, utilizing the latest UVM methodologies and verification frameworks. You will contribute to the planning, testbench development, functional verification, and coverage closure for complex IP blocks and subsystems in next-gen silicon products.
Key Responsibilities:
- Develop and execute RTL verification plans for Ethernet and SerDes IPs using SystemVerilog UVM.
- Define functional coverage metrics and follow coverage-driven verification practices.
- Create, integrate, and maintain testbenches, test plans, and verification environments.
- Collaborate with design teams to review specifications and resolve issues during development.
- Perform block-, sub-system-, and top-level verification to ensure design correctness.
- Debug complex functional issues and drive to root cause efficiently.
- Collaborate with post-silicon validation teams as needed.
- Support integration of C-reference models in SV/UVM testbenches.
- Participate in gate-level simulations with SDF annotation and performance analysis.
Required Qualifications:
- Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.
- 6+ years of hands-on experience in RTL design verification.
- Strong expertise in UVM/VMM methodologies and experience with major EDA simulation/debug tools.
- Proven experience with functional coverage-based constrained-random verification.
- Proficient in scripting languages such as Perl, Python, or Shell.
- Familiar with gate-level simulation flows, including SDF annotation and timing debugging.
- Strong analytical, debugging, and communication skills.
- Ability to work in a collaborative, fast-paced, global team environment.
Preferred/Bonus Skills:
- Knowledge of IEEE 802.3 Ethernet PHY clauses (e.g., Cl.72, 93, 91).
- Experience in high-speed SerDes IP verification.
- Strong understanding of PCIe Gen3 and above, including system-level architecture for PCIe/CXL-based designs.
- Hands-on experience in verifying PLL calibration, mixed-signal interfaces, and multi-clock/reset domain designs.
- In-depth knowledge of PLLs, CDR concepts, AMS interfaces, and networking IPs.
- Experience in taking IPs through full verification lifecycle, from spec to signoff.
Why Join Us?
- Be part of a world-class semiconductor team working on next-generation networking technologies.
- Gain exposure to high-speed SerDes, PCIe, Ethernet, and AMS interfaces in real silicon tape-outs.
- Collaborate with some of the most talented engineers in the industry and help shape the future of communication infrastructure.